Sigma-delta analog-to-digital converters (ADCs) provide for a means to achieve high resolution and low distortion at a relatively low cost compared to traditional Nyquist converters. The high resolution is achieved by oversampling the input signal and shaping the quantization noise in the band of interest into higher frequency region. The higher frequency noise can then be digitally filtered out by the subsequent digital filter stages. The resulting data is then down sampled to the desired sample rate at the output of the converter.
Typically, an audio sigma-delta ADC is implemented using discrete-time circuits such as switched capacitors for the following reasons. Switched capacitor circuits, typically used in the implementation of the first integrator, offer low sensitivity to clock jitter and is readily scalable with sampling rate. Moreover, tracking of coefficients is inherently good due to good matching of capacitors. However, due to the discrete-time nature, the converter suffers from harmonic distortion primarily caused by signal-dependent glitches captured by the sampling capacitors of the first integrator. In highly-integrated circuits such as a digital signal processor (DSP) with on-chip converters, it is very difficult to contain these undesirable glitches since the DSP is running at a much higher clock rate than the converter. Furthermore, for high performance converters, over 100 dB of signal-to-noise ratio (SNR), the sampling capacitors have to be large to reduce the thermal noise. When such large capacitors sample the input voltage, they emit current glitches back into the signal source which leads to electromagnetic interference (EMI).
Instead of implementing the first integrator by switched capacitors, the integrator can be implemented using real resistors and capacitors, such as in the implementation of a continuous-time integrator. The U.S. patent to Sooch et al. (U.S. Pat. No. 5,079,550), hereinafter Sooch, provides for such a combination of continuous-time and discrete integrators in a sigma-delta ADC.
FIG. 1 illustrates a block diagram outlining Sooch's setup 100 comprising summer circuit 101, continuous-time integrator 102, discrete-time integrator(s) 104, quantizer 106, and current feedback digital-to-analog converter (DAC) 108. An analog input signal is connected to the positive input of a summing circuit or summer 101, with the output of summer 101 being connected to the input of loop filter 105, which is also the input to the continuous-time integrator 102. The output of the continuous-time integrator 102 is converted to a discrete-time signal. Connected to the other side of continuous-time integrator 102 is a discrete time integrator 104, wherein the output of the discrete time integrator 104 forms the output of the analog loop filter 105 and is connected to the input of quantizer 106, which, in this example, is a one bit analog-to-digital converter. The output of quantizer 106 forms the output and also forms the input to DAC 108, with the output of DAC 108 being connected to the negative input of summer 101.
Due to the nature of the continuous-time setup of the first stage, any glitches happening in the first stage are averaged out over the clock period instead of being sampled. Hence, the negative effect of these glitches on the performance of the converter is greatly reduced. This is a major advantage of continuous-time versus discrete-time implementations. Moreover, since the input impedance is purely resistive (if the feed forward path from the input is eliminated), the circuit does not emit high frequency current glitches back to the external source. The setup of Sooch yields a much lower electromagnetic interference (EMI) compared to a switched capacitor implementation. But, the Sooch setup of FIG. 1 suffers from various pitfalls, some of which are addressed below.
A major drawback associated with the combination of continuous-time and discrete-time implementation described above is that the RC time constant, or integrator gain varies significantly with process, temperature, and power supply variation. Variation in the RC product changes the noise transfer function of the loop and leads to degradation in performance of the converter.
Another disadvantage associated with such an implementation is that the RC time constant also changes with the period of the master clock of the converter which clocks the switched-capacitor network in the second stage. This essentially limits the converter operation to one particular sampling rate.
Yet another disadvantage associated with the continuous-time implementation is that the continuous-time feedback DAC has inter-symbol-interference (ISI) which dominates the harmonic distortion of the overall performance of the ADC.
An attempt to solve this problem was presented in the article by Xia et al. entitled, “An automatic tuning structure for continuous-time sigma-delta ADC and high precision filters”. Xia et al. addressed stabilizing the RC product via a discrete tuning approach. FIG. 2 illustrates a simplified diagram of the prior art tuning technique as taught by Xia et al. The setup of FIG. 2 comprises reference current source 202, programmable capacitor bank 204, fixed capacitor 206, comparator 208, and tuning logic circuit 210. By calibrating the voltage at the capacitor output to a fixed voltage, the circuit produces a control code that will control both the programmable capacitor array of the tuning circuit and the programmable capacitor array of the first stage continuous-time integrator. Xia's technique suffers from a disadvantage with respect to the coarse quantization step size of the counter, which is not suitable for high precision sigma-delta ADCs. Furthermore, the use of programmable capacitor array 204 also limits the tuning to a narrow range, hence not suitable for the large variation of sampling rate required in audio ADCs.
FIG. 3 shows a conventional differential implementation of a continuous-time first stage in a sigma-delta ADC. It consists of an amplifier 300, a pair of capacitors 302, 304, a pair of input resistors 306, 308, and a feedback DAC, 310. In normal operation mode, the input voltage is converted to current via the input resistors 306, 308. The feedback DAC 310 is controlled by the digital output of the converter. As mentioned before, the low frequency content of the digital output tracks with the input. Hence, the error current, the difference between the input current and the output of the DAC, is mostly high frequency shaped noise. This noise is integrated by the capacitors 302, 304 and then sampled by the subsequent switched capacitor integrator.
Whatever the precise merits, features, and advantages of the above discussed prior art implementations, none of them achieves or fulfills the purposes of the present invention.